This application claims priority to and the benefit of Korea Patent Application No. 2002-0015438 filed on Mar. 21, 2002 in the Korean Intellectual Property Office, the contents of which are incorporated herin by reference.
(a) Field of the Invention
The present invention relates to an organic electroluminescence (hereinafter, xe2x80x9cELxe2x80x9d) display and a scan driver, and, more particularly, to an organic EL display and a scan driver with low power consumption.
(b) Description of the Related Art
In general, an organic EL display is a display that emits light by electrical excitation of fluorescent organic compound and displays images by driving each of Mxc3x97N organic luminescent cells with voltage or current.
The organic cell has a structure of an anode (ITO), an organic thin film and a cathode layer (metal). The organic thin film is formed as a multi-layered structure including an emission layer (xe2x80x9cEMLxe2x80x9d), an electron transport layer (xe2x80x9cETLxe2x80x9d), and a hole transport layer (xe2x80x9cHTLxe2x80x9d) so as to increase luminescence efficiency by balancing electron and hole concentrations. In addition, it can include an electron injection layer (xe2x80x9cEILxe2x80x9d) and a hole injection layer (xe2x80x9cHILxe2x80x9d) separately.
Organic EL displays that use organic luminescent cells like the above are configured as a passive matrix or an active matrix that includes thin film transistors (TFTs). In the passive matrix configuration, organic luminescent cells are formed between anodes and cathodes lines that cross each other and are driven by driving those lines. While in the active matrix configuration, each organic luminescent cell is coupled to a TFT usually through ITO electrode and are driven by controlling the gate voltage of the corresponding TFT.
The organic EL display is generally composed of an organic EL display panel, a scan driver, and a data driver. The organic EL display panel includes a plurality of data lines transmitting data signals representing image signals, a plurality of scan lines transmitting selection signals and pixel circuits provided in pixel areas defined by two adjacent data lines and two adjacent scan lines. When the scan driver applies the selection signals to the scan lines, transistors are turned on by the selection signals, and then, the data signals representing the image signals are applied to gates of driving transistors from the data driver through the data lines, and currents flow through organic EL devices via the transistors in correspondence to the data signals applied to the gates thereof. Thereby, lights are emitted.
In this case, as shown in FIG. 1A, the scan driver is composed of master-slave type flip-flops and NAND gates, and each flip-flop includes four inverters as shown in FIG. 1B. If inverters and NAND gates composed of PMOS transistors or NMOS transistors, which are easy to manufacture compared with CMOS transistors, are used, static currents flow.
FIGS. 2A and 2B are circuit diagrams to represent output parts where the static currents are generated when PMOS transistors or NMOS transistors are used in the inverters or NAND gates.
As shown in FIG. 2A, in the case where logic circuits are composed of PMOS transistors, when a load is attached to GND side, and output Vout is high level, the static currents flow. As shown in FIG. 2B, in the case where logic circuits are composed of NMOS transistors, when a load is attached to VDD side, and output Vout is low level, the static currents flow. Accordingly, when the inverter using PMOS transistors has a low level input and when the NAND gate using PMOS transistors has at least one low level input, the output thereof is high level, and thereby the currents flow. However, in case of a flip-flop composed of four inverters, two inverters receive low level inputs and the other two inverters receive high level inputs. Thus, the static currents always flow in the half of the inverters within the flip-flop.
In the organic EL display panel, so as to use PMOS transistors connected to the scan lines as normally-off switches, inputs applied to the PMOS transistors, i.e., outputs of NAND gates (in case of being composed of PMOS transistors) must become high levels. Accordingly, the static currents flow in the NAND gates during most of time.
When the static currents flow as above, there is a problem that static power loss is increased, and thereby power consumptions are increased in the scan driver.
In accordance with the present invention power consumption is decreased by reducing static currents in a scan driver.
A scan driver is divided into several parts and a clear signal is applied to a non-operating scan driver.
An organic EL display according to the present invention includes an organic EL display panel, a data driver applying data signals to data lines, and a scan driver applying selection signals to scan lines. The organic EL display panel includes a plurality of scan lines transmitting selection signal, a plurality of data lines transmitting data signals representing image signals, and a plurality of pixel circuits coupled to the scan lines and the data lines.
The scan driver is composed of more than two scan driving units and a selection controller generating clear signals, and each scan driving unit includes a plurality of flip-flops coupled with each other in series and a plurality of buffer units receiving outputs of the flip-flops to drive the respective scan lines. Each of the flip-flops is composed of a plurality of logic gates (NOR gates or NAND gates) and a plurality of switching elements. The clear signals keep outputs of logic gates of scan driving units as a constant value for the scan driving units not to generate the selection signal.
The flip-flop is composed of a first to a fourth logic gates, and the first logic gate receives the clear signal and output of the previous flip-flop, inputted through a first switching element, as input. A second logic gate receives the output of the first logic gate and the clear signal as input, and the output terminal of the second logic gate is coupled via a second switching element to the output of the previous flip-flop inputted through the first switching element. A third logic gate receives the clear signal and the output of the first logic gate inputted through a third switching element as input, and output of the third logic gate becomes output of the flip-flop. A fourth logic gate receives the clear signal and the output of the third logic gate, and the output terminal of the fourth logic gate is coupled via a fourth switching element to the output of the first logic gate inputted through the third switching element.
In addition, the selection controller may further generate reset signals for setting initial values of the scan driving units. The first and the fourth logic gates preferably further receive the reset signals as inputs.
Furthermore, the buffer unit preferably includes a fifth logic gate receiving output of the flip-flop and the clear signal. The buffer unit may include an inverter coupled to output terminal of the fifth logic gate and a buffer coupled to output terminal of the inverter.
The first to the fifth logic gates are preferably composed of the same conductive type thin film transistors.
The first to the fifth logic gates are NOR gates, which may be composed of PMOS transistors. Or, the first to the fifth logic gates are NAND gates, which may be composed of NMOS transistors.
A method of driving the organic EL display in accordance with the present invention includes: dividing the scan driver into a plurality of scan driving units, applying a first clear signal, with level for making outputs of the logic gates constant regardless of other inputs, to the other scan driving units while the selection signal is generated from a n-th scan driving unit, and applying a second clear signal with level opposite to that of the first clear signal to the n-th scan driving unit; applying the second clear signal to a (n+1)-th scan driving unit adjacent to the n-th scan driving unit before the (n+1)-th scan driving unit receives the selection signal outputted from the last flip-flop of the n-th scan driving unit; and applying the first clear signal to the n-th scan driving unit when the selection signal begins to be outputted from the (n+1)-th scan driving unit.
In addition, a reset signal for setting an initial value of the (n+1)-th scan driving unit may be applied thereto before the second clear signal is applied to the (n+1)-th scan driving unit.
The logic gates are preferably NOR gates composed of PMOS transistors. Or, the logic gates are NAND gates composed of NMOS transistors.